Chemical vapor deposition of titanium

ABSTRACT

A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.

RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. applicationSer. No. 09/030,705, filed Feb. 25, 1998, which is hereby incorporatedby reference in its entirety.

FIELD OF THE INVENTION

[0002] The present invention relates to a method for manufacturingsemiconductor devices, and more particularly, to a method for depositingtitanium layers on a substrate.

BACKGROUND OF THE INVENTION

[0003] Device density in integrated circuits (ICs) is constantly beingincreased. To enable the increase in density, device dimensions arebeing reduced. As the dimensions of device contacts get smaller, devicecontact resistance increases, and device performance is adverselyaffected. Methods for decreasing device contact resistance in ICs areneeded to obtain enhanced device and IC performance.

[0004] Device contacts with reduced resistance may be created by formingcertain metals on a silicon semiconductor base layer. These metals reactwith the underlying silicon, for example, to form suicides. Silicidedevice contacts are desirable because they reduce the native oxide onsilicon. The native oxide is undesirable because it increases thecontact resistance.

[0005] In one embodiment, titanium is used to form silicide devicecontacts for two reasons. First, titanium silicide has superiorgettering qualities. Also, titanium silicide forms low resistancecontacts on both polysilicon and single-crystal silicon.

[0006] Titanium silicide device contacts are normally formed with thefollowing process. First, a thin layer of titanium is formed on top ofthe silicon base layer, such as a substrate. The titanium adjoins activeregions exposed by contact holes in an isolating layer, such as anoxide, above the silicon base layer. Then, the silicon base layer isannealed. As a result, the titanium reacts with the active regions ofsilicon to form titanium silicide.

[0007] However, because titanium cannot be readily deposited in a pureform, additional processing steps are required to form titanium silicidedevice contacts. Titanium precursors, such as titanium tetrachloride,are commonly available and can be used to form titanium. Titaniumtetrachloride, though, can only be reduced at temperatures exceeding1000 degrees Celsius with certain reducing agents. At thesetemperatures, the silicon base layer will be damaged. Therefore, thereis a need for a method of forming titanium from titanium precursors atlower temperatures.

[0008] Furthermore, the resistance of device contacts can be adverselyincreased by conductive layers coupled between the device contacts andother components. The conductive layers may be formed by the same metallayer used to form the device contacts. As device dimensions shrink, thecontact holes become relatively deeper and narrower. Also, the walls ofthe contact holes become steeper, and closer to vertical. As a result,most metal deposition techniques form conductive layers havingrelatively small step coverage, and hence relatively high resistance.Step coverage is the ratio of the minimum thickness of a film as itcrosses a step, to the nominal thickness of the film on flat regions,where thickness is generally measured perpendicular to the surfaces ofthe step and flat regions, and where the resultant value is usuallyexpressed as a percentage. Thus, the effective contact resistance isincreased at lower values of step coverage. Therefore, there is also aneed for a method of forming conductive layers having increased stepcoverage to reduce effective device contact resistance.

[0009] Conformal layers of titanium having good step coverage have beenpreviously formed at lower temperatures with chemical vapor deposition.Such techniques are disclosed in U.S. Pat. Nos. 5,173,327, 5,273,783 and5,278,100, which are hereby incorporated by reference. However,alternative, effective and efficient techniques for forming titaniumfilms are desired.

SUMMARY OF THE INVENTION

[0010] The present invention provides a method, and a correspondingresulting structure, for forming conformal titanium films supported on asubstrate of an integrated circuit (IC) by forming a seed layersupported by the substrate, and then reducing a titanium precursor withthe seed layer. In one embodiment, the seed layer comprises a main groupelement selected from the group consisting of zinc, cadmium, mercury,aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic andantimony. The seed layer is formed by combining a first precursor and areducing agent by chemical vapor deposition (CVD). Then, titanium isformed by combining a second precursor with the seed layer by CVD.

[0011] In another embodiment, the present invention may further comprisethe step of annealing the titanium to form titanium silicide.

[0012] In another embodiment, forming the seed layer further comprisesforming a seed layer according to the following chemical process (I):

MR_(x)+H₂→M+alkanes,

[0013] wherein:

[0014] M is a main group element selected from the group consisting ofzinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon,germanium, lead, arsenic and antimony;

[0015] R is an alkyl group; and

[0016] x is some integer value determined by the valence of M.

[0017] In one embodiment, chemical process (I) is performed at atemperature between approximately 100 and 600 degrees Celsius.

[0018] In yet another embodiment, the step of forming titanium furthercomprises the step of combining the seed layer with the second precursorthat is titanium tetrachloride according to the following chemicalprocess (II):

TiCl₄+M→Ti+MCl_(x).

[0019] In one embodiment, chemical process (II) is performed at atemperature between approximately 100 and 600 degrees Celsius.

[0020] In yet another embodiment, titanium may be formed in a singlestep according to the following chemical process (III):

TiCl₄+M (source)→Ti+MCl_(x)

[0021] In one embodiment, chemical process (III) is performed at atemperature between approximately 100 and 700 degrees Celsius.

[0022] In yet a further embodiment, the present invention may be an ICcomprising a layer of a titanium alloy, coupled to a titanium silicidecontact. In yet another embodiment, the present invention may be amemory comprising a memory array operatively coupled to a controlcircuit and an I/O circuit. The memory array, control circuit and I/Ocircuit comprise a layer of a titanium alloy coupled to titaniumsilicide contacts. In yet another embodiment, the titanium alloy maycomprise titanium and an element selected from the group consisting ofzinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon,germanium, lead, arsenic and antimony. In still another embodiment, thetitanium alloy may comprise titanium and zinc.

[0023] It is a benefit of the present invention that high step coveragemetal layers can be formed. Further features and advantages of thepresent invention, as well as the structure and operations of variousembodiments of the present invention, are described in detail below withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES

[0024]FIG. 1A is a cross-sectional view of a contact hole that has beenetched through an insulative layer to an underlying semiconductorsubstrate.

[0025]FIG. 1B is a cross-sectional view of the contact hole of FIG. 1A,comprising titanium and titanium silicide film.

[0026]FIG. 2 is a cross-sectional view of the contact hole of FIG. 1A,comprising a film of second reducing agent.

[0027]FIG. 3A is a cross-sectional view of the contact hole of FIG. 1A,comprising a titanium film.

[0028]FIG. 3B is a block diagram of a memory.

DETAILED DESCRIPTION OF THE INVENTION

[0029] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable persons skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present invention. The terms wafer and substrate used inthe following description include any semiconductor-based structurehaving an exposed surface with which to form the integrated circuitstructure of the invention. Wafer and substrate are used interchangeablyto refer to semiconductor structures during processing, and may includeother layers that have been fabricated thereupon. Both wafer andsubstrate include doped and undoped semiconductors, epitaxialsemiconductor layers supported by a base semiconductor or insulator, aswell as other semiconductor structures well known to one skilled in theart. The following detailed description is, therefore, not to be takenin a limiting sense, and the scope of the present invention is definedonly by the appended claims.

[0030] The subsequently described methods will be in the context ofusing zinc as a metal seed layer. However, other seed layers aresuitable for use with the various embodiments of the invention, as willbe described.

[0031] In order to manufacture a device contact in an integrated circuit19, a contact hole 10, as shown in FIG. 1A, is etched through aninsulating layer 12, such as borophosphosilicate glass (BPSG) or silicondioxide (SiO₂). As a result, an active region 17 of underlyingsemiconductor base layer or substrate 14, is exposed. A device contactis then formed on the exposed active region 17 in the following manner.

[0032] Chemical vapor deposition (CVD) is used to form a conformal layerof titanium or titanium alloy on the integrated circuit 19 by asubsequently described method. CVD is further described in U.S. Pat. No.5,278,100. In one embodiment, the conformal layer has a step coverage ofat least one hundred percent in the contact hole 10, even for a highaspect ratio contact hole (i.e., a contact hole that is much deeper thanit is wide). As a result, a low resistance layer of titanium or titaniumalloy 16 is formed on the insulating layer 12, as shown in FIG. 1B. Aportion of the layer 16 is formed as a low resistance device contact 18of titanium silicide over the active region 17.

[0033] In another embodiment, a cold wall-hot substrate reactor is usedto form the conformal layer of titanium or titanium alloy. In oneembodiment, a cold wall-hot substrate reactor is used for blanketdepositions as this design is efficient in regard to precursorconsumption. In one embodiment, first, a conformal film of a seed layer22 comprising zinc is deposited on the insulator 12 and substrate 14, asshown in FIG. 2. The seed layer 22 is formed with CVD by combining afirst reducing agent 24 with a first precursor 26, which are injectedinto the CVD reactor which is represented in block form at 29. Inanother embodiment, the seed layer 22 that is zinc may be formed bycombining a first precursor 26 that is a dialkyl zinc or trimethyl zinccompound with a reducing agent 24 that is hydrogen.

[0034] When performing this step, the integrated circuit 19 is mountedon a substrate holder in the CVD reactor 29. The substrate 14 is heatedto a temperature within a range of approximately 100 to 600 degreesCelsius and at a pressure approximately between 1 millitorr and 1atmosphere. Alternatively, the temperature may range from approximately300 to 550 degrees Celsius, or approximately 350 to 450 degrees Celsius.In one embodiment, the temperature is approximately 400 degrees Celsius.Also, alternatively, the pressure may range from approximately 10millitorr to 100 torr. In one embodiment, the pressure is approximately1 torr. A carrier gas of helium, argon or nitrogen may be used at a flowrate of between approximately 1 and 200 sccm. Alternatively, the flowrate may range between approximately 20 sccm and 1 liter. In oneembodiment, the pressure is approximately 200 sccm. The first precursor26 and the reducing agent 24 contact the heated silicon base layer andinsulating layer 12, and form the seed layer 22 on the integratedcircuit 19. This chemical process (I) is exemplified below:

ZnR₂(gas)+H₂ (gas)→Zn (solid)+alkanes (gas),

[0035] where R is an alkyl group.

[0036] First reaction products 28, such as gaseous alkanes, resultingfrom the formation of the seed layer 22 exit from the CVD reactor 29through an exhaust manifold. The thickness of the seed layer 22 formedon the integrated circuit 19 is between approximately 5 and 50angstroms. However, the present invention envisions forming a seed layer22 that is thicker.

[0037] Next, the seed layer 22 is converted to a layer 16 of titanium ora titanium alloy. As illustrated in FIG. 3A, a titanium precursor 32,such as titanium tetrachloride, is combined with the seed layer 22 byCVD to form a conformal layer 16 of titanium or titanium alloy in lieuof the seed layer 22.

[0038] When performing this step, the integrated circuit 19 is mountedand heated in the CVD reactor 29 to a temperature within a range ofapproximately 100 to 600 degrees Celsius and at a pressure approximatelybetween 1 millitorr and 1 atmosphere. Alternatively, the temperature mayrange from approximately 100 to 700 degrees Celsius, approximately 300to 550 degrees Celsius, or approximately 350 to 450 degrees Celsius. Inone embodiment, the temperature is approximately 400 degrees Celsius.Also, alternatively, the pressure may range from approximately 10millitorr to 100 torr. In one embodiment, the pressure is approximately1 torr. A carrier gas of helium, argon or nitrogen may be used at a flowof between approximately 1 and 200 sccm. Alternatively, the flow ratemay range between approximately 20 sccm and 1 liter. In one embodiment,the pressure is approximately 200 sccm. When the titanium precursor 32contacts the seed layer 22 on the integrated circuit 19, the compoundsform a conformal layer 16 of titanium or a titanium alloy. The chemicalprocess (II) is exemplified below:

TiCl₄ (gas)+Zn (solid)→Ti (solid)+ZnCl₂ (gas)

[0039] Second reaction products 34 resulting from the formation of thetitanium or titanium alloy exit from the CVD reactor 29 through theexhaust manifold. Part or all of the seed layer 22 is converted to alayer 16 of titanium or titanium alloy. If this process step isconducted for a sufficient period of time, all of the seed layer 22 willbe converted to a layer 16 of titanium. However, if not all of the seedlayer 22 is converted to a layer 16 of titanium, a layer 16 of titaniumalloy, including the seed layer 22, will be formed on the integratedcircuit 19. These steps may be repeated to form thicker layers.

[0040] In another embodiment, the layer 16 of titanium or titanium alloycan be formed during a single CVD step, as exemplified by chemicalprocess (III) below:

TiCl₄+Zn (source)→Ti+ZnCl₂   (III)

[0041] The zinc can be provided from one of many types of sources,including gaseous and solid sources. In one embodiment of such a singleCVD step, the seed and titanium layers 22, 16 can be formedsubstantially simultaneously. The titanium or titanium alloy layer 16can be formed by combining a first precursor 26, such as a dialkyl ortrimethyl zinc compound, with a reducing agent 24, such as hydrogen, anda titanium precursor 32, such as titanium tetrachloride. When performingthe CVD step, the integrated circuit 19 is mounted and heated in the CVDreactor 29 to a temperature within a range of approximately 100 to 600degrees Celsius at a pressure of approximately between 1 millitorr and 1atmosphere. Alternatively, the temperature may range from approximately100 to 700 degrees Celsius, approximately 300 to 550 degrees Celsius, orapproximately 350 to 450 degrees Celsius. In one embodiment, thetemperature is approximately 400 degrees Celsius. Also, alternatively,the pressure may range from approximately 10 millitorr to 100 torr. Inone embodiment, the pressure is approximately 1 torr. A carrier gas ofhelium, argon or nitrogen may be used at a flow rate of betweenapproximately 1 and 200 sccm. Alternatively, the flow rate may rangebetween approximately 20 sccm and 1 liter. In one embodiment, thepressure is approximately 200 sccm. When the first precursor 26 and thereducing agent 24 contact the heated silicon base layer and insulatinglayer 12, they form the seed layer 22 on the integrated circuit 19.Then, when the titanium precursor 32 contacts the seed layer 22, aconformal layer 16 of titanium or titanium alloy is formed on theintegrated circuit. The resulting layer 16 of titanium or titanium alloyhas a thickness between approximately 5 and 50 angstroms. However, thepresent invention envisions forming a thicker layer 16 titanium ortitanium alloy. The chemical process (IV) is exemplified below:

ZnR₂ (gas)+H₂ (gas)+TiCl₄ (gas)→Ti (solid)+ZnCl₂ (gas)+alkanes (gas),

[0042] where R is an alkyl group.

[0043] The reaction products 28, 34 exit from the CVD reactor 29 throughthe exhaust manifold.

[0044] Subsequently, the integrated circuit 19 is annealed at atemperature of between approximately 250 to 750 degrees Celsius.Alternatively, the temperature may range from approximately 250 to 800degrees Celsius. In one embodiment, the temperature is approximately 700degrees Celsius. As a result, the titanium in the layer 16 of titaniumor titanium alloy proximate to the silicon is converted to titaniumsilicide (TiSi, TiSi₂, Ti₃Si₅ or combinations thereof) to form the lowresistance device contact 18. For via level applications, the anneal isnot required. The via comprises a tungsten or aluminum fill on top ofthe layer 16 which is formed on top of a conductor (also represented byreference number 17) with an optional TiN layer therebetween.

[0045] In yet another embodiment, the low resistance device contact 18of titanium silicide may be formed over the active region 17 when thelayer 16 of titanium or titanium alloy is formed by CVD on theintegrated circuit 19 at a temperature of between approximately 250 to750 degrees Celsius. Alternatively, the temperature may range fromapproximately 250 to 800 degrees Celsius. In one embodiment, thetemperature is approximately 700 degrees Celsius. Upon device contact 18formation, additional metal layers, such as titanium nitride andtungsten, may be subsequently formed over the device contact 18 andlayer 16 of titanium or titanium alloy.

[0046] In another embodiment, the integrated circuit 19 is a memory 300in FIG. 3B, such as a dynamic random access memory. The memory 300 mayinclude an array of memory cells 302, control circuit 304, I/O circuit,word line decoder 308, digit, or bit, line decoder 310, and senseamplifier 312 coupled in a manner known to one skilled in the art. Eachof the aforementioned elements of the memory 300 includes contacts 18and layers 16 of titanium, or titanium alloy, formed in the mannerdescribed above.

[0047] As noted above, other seed layers are suitable for use with thevarious embodiments of the invention. In one embodiment, the firstprecursor 26 is an alkane of the form MR,, where M is an elementselected from the group consisting of zinc, cadmium, mercury, aluminum,gallium, indium, tin, silicon, germanium, lead, arsenic and antimony; Ris an alkyl group; and x is some integer value determined by the valenceof M. The value of x is generally equal to a valence of M, e.g.,when Mhas a valence of 3 as does aluminum, x equals 3. M may be capable ofhaving more than one valence. Such alkane precursors may be used to formthe seed layer 22. Chemical process (I) for the formation of seed layer22 may then be written in its more general form:

MR_(x) (gas)+H₂ (gas)→M (solid)+alkanes (gas),   (I)

[0048] wherein:

[0049] M is an element selected from the group consisting of zinc,cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium,lead, arsenic and antimony;

[0050] R is an alkyl group; and

[0051] x is some integer value equal to the valence of M.

[0052] In similar fashion, chemical process (II) for the formation ofthe layer 16 of titanium or titanium alloy may be written more generallyas:

TiCl₄ (gas)+M (solid)→Ti (solid)+MCl_(x) (gas)   (II)

[0053] wherein:

[0054] M is an element selected from the group consisting of zinc,cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium,lead, arsenic and antimony; and

[0055] x is some integer value equal to the valence of M.

[0056] In another embodiment, where the formation of the layer 16 oftitanium or titanium alloy is performed in a single step, chemicalprocess (III) may be written more generally as:

TiCl₄+M (source)→Ti+MCl_(x)   (III)

[0057] wherein:

[0058] M is an element selected from the group consisting of zinc,cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium,lead, arsenic and antimony; and

[0059] x is some integer value equal to the valence of M.

[0060] In a further embodiment, where the formation of the layer 16 oftitanium or titanium alloy is performed in a single CVD step, chemicalprocess (I) may be written more generally as:

MR_(x) (gas)+H₂ (gas)+TiCl₄ (gas)→Ti(solid)+MCl_(x) (gas)+alkanes(gas),  (IV)

[0061] wherein:

[0062] M is an element selected from the group consisting of zinc,cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium,lead, arsenic and antimony;

[0063] R is an alkyl group; and

[0064] x is some integer value equal to the valence of M.

[0065] The various embodiments of the present invention provide highstep coverage, low resistivity titanium silicide device contacts tosilicon, or titanium contacts to metal at the via level, formed at arelatively low temperature. Use of the various alkane precursors permitsformation of a titanium layer without depletion of an underlying siliconor other base layer.

[0066] It is to be understood that the above description is intended tobe illustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reviewing the abovedescription. For example, other titanium precursors, such astetradimethyl amino titanium (TDMAT) can be used to form layers 16 anddevice contacts 18. Additionally, the present invention may beimplemented with any CVD apparatus 29, including hot wall reactors, coldwall reactors, radiation beam assisted reactors, plasma-assistedreactors, and the like. Furthermore, the seed layer 22 may be formed inany manner which provides a desired thickness film. Hence, the scope ofthe invention should, therefore, be determined with reference to theappended claims, along with the full scope of equivalents to which suchclaims are entitled.

What is claimed is:
 1. A method for forming a titanium layer supportedby a substrate, comprising: forming a seed layer supported by thesubstrate by combining a first precursor with a first reducing agent;and forming the titanium layer supported by the substrate by combining atitanium-containing precursor with the seed layer.
 2. A method forforming a titanium layer supported by a substrate, comprising: forming aseed layer supported by the substrate by combining a first precursorwith a first reducing agent, wherein the first precursor is an alkane;and forming the titanium layer supported by the substrate by combining atitanium-containing precursor with the seed layer.
 3. The method ofclaim 1, further comprising annealing the titanium layer to formtitanium silicide.
 4. The method of claim 1, wherein forming a seedlayer comprises forming a seed layer in accordance with the followingchemical process (I): MR_(x)+H₂→M+alkanes,   (I) wherein: M is anelement selected from the group consisting of zinc, cadmium, mercury,aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic andantimony; R is an alkyl group; and x is some integer value equal to thevalence of M.
 5. The method of claim 1, wherein forming a seed layercomprises forming a zinc seed layer in accordance with the followingchemical process (I): ZnR₂+H₂→Zn+alkanes,   (I) wherein: R is an alkylgroup.
 6. The method of claim 4, wherein forming a seed layer isperformed at a temperature between approximately 100 and 600 degreesCelsius.
 7. The method of claim 1, wherein forming the titanium layercomprises forming the titanium layer in accordance with the followingchemical process (II): TiCl₄+M→Ti+MCl_(x)   (II) wherein: M an elementselected from the group consisting of zinc, cadmium, mercury, aluminum,gallium, indium, tin, silicon, germanium, lead, arsenic and antimony;and x is some integer value equal to the valence of M.
 8. The method ofclaim 1, wherein forming the titanium layer comprises forming thetitanium layer in accordance with the following chemical process (II):TiCl₄+Zn→Ti+ZnCl₂.   (II)
 9. The method of claim 7, wherein forming thetitanium layer in accordance with chemical process (II) is performed ata temperature between approximately 100 and 600 degrees Celsius.
 10. Themethod of claim 1, wherein forming the titanium layer further comprisesforming titanium silicide.
 11. The method of claim 10, wherein formingtitanium silicide comprises forming titanium silicide at a temperatureof between approximately 250 to 750 degrees Celsius.
 12. The method ofclaim 1, wherein forming the titanium layer comprises forming thetitanium layer comprising a titanium alloy.
 13. The method of claim 12,wherein forming the titanium layer comprising a titanium alloy comprisesa titanium alloy containing titanium and an element selected from thegroup consisting of zinc, cadmium, mercury, aluminum, gallium, indium,tin, silicon, germanium, lead, arsenic and antimony.
 14. The method ofclaim 12, wherein forming the titanium layer comprising a titanium alloycomprises a titanium alloy containing titanium and zinc.
 15. A methodfor forming a titanium layer on an integrated circuit, comprising:forming a seed layer on the integrated circuit by combining a firstprecursor with a reducing agent with chemical vapor deposition (CVD);and forming the titanium layer on the integrated circuit by combiningthe seed layer with a second precursor with CVD; wherein the seed layeris formed according to the following chemical process (I):MR_(x)+H₂→M+alkanes, wherein: M an element selected from the groupconsisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin,silicon, germanium, lead, arsenic and antimony; R is an alkyl group; andx is some integer value equal to the valence of M; wherein chemicalprocess (I) is performed at a temperature greater than 400 degreesCelsius; and wherein the titanium layer is formed according to thefollowing chemical process (II): TiCl₄+M→Ti+MCl_(x),   (II) whereinchemical process (II) is performed at a temperature greater than 400degrees Celsius.
 16. A method for forming a titanium layer on anintegrated circuit, comprising: forming a seed layer on the integratedcircuit by combining a first precursor with a reducing agent withchemical vapor deposition (CVD); forming the titanium layer on theintegrated circuit by combining the seed layer with a second precursorwith CVD; wherein the seed layer is zinc, and formed according to thefollowing chemical process (I): ZnR₂+H₂→Zn+alkanes,   (I) wherein R isan alkyl group and chemical process (I) is performed at a temperaturegreater than 400 degrees Celsius; and wherein the titanium layer isformed according to the following chemical process (II):TiCl₄+Zn→Ti+ZnCl₂,   (II) wherein chemical process (II) is performed ata temperature greater than 400 degrees Celsius.
 17. The method of claim15, further comprising annealing the titanium layer to form titaniumsilicide.
 18. The method of claim 15, wherein forming the titanium layerfurther comprises forming titanium silicide.
 19. The method of claim 18,wherein forming the titanium silicide comprises forming titaniumsilicide at a temperature of between approximately 250 to 750 degreesCelsius.
 20. The method of claim 15, wherein forming the titanium layercomprises forming the titanium layer comprising a titanium alloy. 21.The method of claim 15, wherein forming the titanium layer comprising atitanium alloy comprises a titanium alloy containing titanium and anelement selected from the group consisting of zinc, cadmium, mercury,aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic andantimony.
 22. The method of claim 15, wherein forming the titanium layercomprising a titanium alloy comprises a titanium alloy containingtitanium and zinc.
 23. A method for forming a titanium layer supportedby a substrate, comprising: forming a seed layer supported by thesubstrate by combining a first precursor with a first reducing agent,wherein the first precursor is an alkane and wherein the alkanecomprises an element selected from the group consisting of zinc,cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium,lead, arsenic and antimony; and forming the titanium layer supported bythe substrate by combining a titanium-containing precursor with the seedlayer.
 24. A chemical vapor deposition method of providing a layer oftitanium on an integrated circuit within a chemical vapor deposition(CVD) reactor, the method comprising: injecting a first precursor andreducing agent in the CVD reactor; forming a seed layer on theintegrated circuit from reaction of the first precursor and the reducingagent, wherein the first precursor is an alkane; injecting a secondprecursor in the CVD reactor; and forming the titanium layer on theintegrated circuit from reaction of the second precursor and the seedlayer.
 25. A chemical vapor deposition method of providing a layer oftitanium on an integrated circuit within a chemical vapor deposition(CVD) reactor, the method comprising: injecting a first precursor andreducing agent in the CVD reactor; forming a seed layer on theintegrated circuit from reaction of the first precursor and the reducingagent, wherein the first precursor is an alkane and wherein the alkanecomprises an element selected from the group consisting of zinc,cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium,lead, arsenic and antimony; injecting a second precursor in the CVDreactor; and forming the titanium layer on the integrated circuit fromreaction of the second precursor and the seed layer.
 26. A chemicalvapor deposition method of providing a layer of titanium on anintegrated circuit within a chemical vapor deposition (CVD) reactor, themethod comprising: injecting a first precursor and reducing agent in theCVD reactor; forming zinc on the integrated circuit from a reaction ofthe first precursor and the first reducing agent; injecting a secondprecursor in the CVD reactor; and forming the titanium layer on theintegrated circuit from a reaction of the second precursor and the zinc.27. The method of claim 24, further comprising annealing the titaniumlayer to form titanium silicide.
 28. The method of claim 24, whereinforming the seed layer is in accordance with the following chemicalprocess (I): MR_(x)+H₂→M+alkanes,   (I) wherein: M is an elementselected from the group consisting of zinc, cadmium, mercury, aluminum,gallium , indium, tin, silicon, germanium, lead, arsenic and antimony; Ris an alkyl group; and x is some integer value equal to the valence ofM.
 29. The method of claim 26, wherein forming the zinc is in accordancewith the following chemical process (I): ZnR₂+H₂→Zn+alkanes;   (I)wherein: R is an alkyl group.
 30. The method of claim 28, whereinforming the seed layer comprises forming the seed layer according tochemical process (I) at a temperature between approximately 100 and 600degrees Celsius.
 31. The method of claim 28, wherein forming thetitanium layer comprises forming the titanium layer in accordance withthe following chemical process (II): TiCl₄+M→Ti+MCl_(x)   (II)
 32. Themethod of claim 29, wherein forming the titanium layer comprises formingthe titanium layer in accordance with the following chemical process(II): TiCl₄+Zn→Ti+ZnCl₂.   (II)
 33. The method of claim 31, whereinforming the titanium layer comprises forming the titanium layeraccording to chemical process (II) at a temperature betweenapproximately 100 and 600 degrees Celsius.
 34. The method of claim 24,wherein forming the titanium layer further comprises forming titaniumsilicide.
 35. The method of claim 34, wherein forming titanium silicidecomprises forming titanium silicide at a temperature of betweenapproximately 250 to 750 degrees Celsius.
 36. The method of claim 24,wherein forming the titanium layer further comprises forming a titaniumalloy containing titanium and an element selected from the groupconsisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin,silicon, germanium, lead, arsenic and antimony.
 37. The method of claim26, wherein forming the titanium layer further comprises forming atitanium zinc alloy layer.
 38. A method for forming a titanium layersupported by a substrate, comprising forming the titanium layeraccording to the following chemical process (III):TiCl₄+M(source)→Ti+MCl_(x) wherein: M is an element selected from thegroup consisting of zinc, cadmium, mercury, aluminum, gallium, indium,tin, silicon, germanium, lead, arsenic and antimony; and x is someinteger value equal to the valence of M.
 39. A method for forming atitanium layer supported by a substrate, comprising forming the titaniumlayer according to the following chemical process (III):TiCl₄+Zn→Ti+ZnCl₂.   (III)
 40. The method of claim 38, furthercomprising annealing the titanium layer to form titanium silicide.
 41. Amethod for forming a titanium layer supported by a substrate, comprisingforming the titanium layer according to the following chemical process(IV): MR_(x)+H₂+TiCl₄→Ti+MCl_(x)+alkanes,   (IV) wherein: M is anelement selected from the group consisting of zinc, cadmium, mercury,aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic andantimony; R is an alkyl group; and x is some integer value equal to thevalence of M.
 42. A method for forming a titanium layer supported by asubstrate, comprising forming the titanium layer according to thefollowing chemical process (IV): ZnR₂+H₂+TiCl₄→Ti+ZnCl₂+alkanes,   (IV)wherein: R is an alkyl group.
 43. The method of claim 41, whereinforming the titanium layer comprises forming the titanium layercomprising a titanium alloy.
 44. An integrated circuit comprising: alayer of a titanium alloy, wherein the titanium alloy comprises titaniumand an element selected from the group consisting of zinc, cadmium,mercury, aluminum, gallium, indium, tin, silicon, germanium, lead,arsenic and antimony; and a titanium silicide contact coupled to thelayer.
 45. The integrated circuit of claim 34, wherein the titaniumalloy comprises titanium and zinc.
 46. A memory, comprising: a memoryarray; a control circuit, operatively coupled to the memory array; anI/O circuit, operatively coupled to the memory array; and wherein thememory array, control circuit and I/O circuit each comprise: a layer ofa titanium alloy, wherein the titanium alloy comprises titanium and anelement selected from the group consisting of zinc, cadmium, mercury,aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic andantimony; and a titanium silicide contact coupled to the layer.
 47. Thememory of claim 46, wherein the titanium alloy comprises titanium andzinc.
 48. A contact, comprising: a titanium alloy layer formed overlyingwalls of a contact hole; and a titanium silicide layer formed overlyingan exposed silicon base layer of the contact hole.
 49. A contact,comprising: a titanium alloy layer formed overlying walls of a contacthole, wherein the titanium alloy layer comprises titanium and an elementselected from the group consisting of zinc, cadmium, mercury, aluminum,gallium, indium, tin, silicon, germanium, lead, arsenic and antimony;and a titanium silicide layer formed overlying an exposed silicon baselayer of the contact hole.
 50. A contact, comprising: a titanium alloylayer formed overlying walls of a contact hole, wherein the titaniumalloy layer comprises titanium and zinc; and a titanium silicide layerformed overlying an exposed silicon base layer of the contact hole. 51.A via, comprising: a titanium alloy layer formed overlying walls and anexposed base layer of a contact hole; and a fill coupled to the titaniumalloy layer, wherein the fill comprises a metal selected from the groupconsisting of tungsten and aluminum.
 52. The via of claim 51, whereinthe titanium alloy layer comprises titanium and zinc.
 53. A via,comprising: a titanium alloy layer formed overlying walls and an exposedbase layer of a contact hole, wherein the titanium alloy layer comprisestitanium and an element selected from the group consisting of zinc,cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium,lead, arsenic and antimony; and a fill coupled to the titanium alloylayer, wherein the fill comprises a metal selected from the groupconsisting of tungsten and aluminum.
 54. The via of claim 51, furthercomprising a titanium nitride layer interposed between the titaniumalloy layer and the fill.
 55. A via, comprising: a titanium alloy layerformed overlying walls and an exposed base layer of a contact hole; afill comprising a metal selected from the group consisting of tungstenand aluminum; and a titanium nitride layer interposed between thetitanium alloy layer and the fill.
 56. A via, comprising: a titaniumalloy layer formed overlying walls and an exposed base layer of acontact hole, wherein the titanium alloy layer comprises titanium and anelement selected from the group consisting of zinc, cadmium, mercury,aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic andantimony; a fill comprising a metal selected from the group consistingof tungsten and aluminum; and a titanium nitride layer interposedbetween the titanium alloy layer and the fill.
 57. A memory device,comprising: a memory array; a control circuit operatively coupled to thememory array; and an I/O circuit operatively coupled to the memoryarray; wherein at least one of the memory array, control circuit and I/Ocircuit comprises a contact having a titanium alloy layer formedoverlying walls of a contact hole and a titanium silicide layer formedoverlying an exposed silicon base layer of the contact hole.
 58. Amemory device, comprising: a memory array; a control circuit operativelycoupled to the memory array; and an I/O circuit operatively coupled tothe memory array; wherein at least one of the memory array, controlcircuit and I/O circuit comprises a via having a titanium alloy layerformed overlying walls and an exposed base layer of a contact hole and afill coupled to the titanium alloy layer, wherein the fill comprises ametal selected from the group consisting of tungsten and aluminum.
 59. Amemory device, comprising: a memory array; a control circuit operativelycoupled to the memory array; and an I/O circuit operatively coupled tothe memory array; wherein at least one of the memory array, controlcircuit and i/O circuit comprises a titanium layer, wherein the titaniumlayer is produced using a method, the method comprising: forming a seedlayer supported by a substrate by combining a first precursor with afirst reducing agent; and forming the titanium layer supported by thesubstrate by combining a titanium-containing precursor with the seedlayer.